1. Field of the Invention
The present invention relates generally to integrated circuits and, more particularly, to semiconductor transistor structures having improved source/drain junction performance.
2. Description of the Related Art
As the demand for faster, smaller, and more densely packed integrated circuit designs continue to increase, a greater burden is placed on design engineers to improve upon the design of standard CMOS transistors. Dominant limitations in scaling down the size of transistors are directly linked to increasing parasitic source/drain junction capacitances, tight thermal budget constraints for backend processing, hot carrier damage, and the possibility of punch-through between the source/drain as gate lengths continue to shrink. These limitations are therefore the driving force that has intensified drain engineering in high performance digital CMOS technology transistor design. Recent studies have proven that very shallow junction formation (around 0.1 micron or less) is necessary for drain engineering to be feasible in quarter-micron technology devices and below, which is common in current CMOS technology. To illustrate some of the conventional transistor devices and their associated limitations, reference is now drawn to FIGS. 1A through 1E.
FIG. 1A shows a cross-sectional view of an LDD (lightly doped drain) transistor device 100 fabricated over a semiconductor substrate 102. The LDD transistor device 100 is shown having diffusion regions 104a and 104b, which respectively define the source and drain of the transistor device 100. Between the source and drain, a gate structure including a gate oxide 108 and a gate electrode 109 is fabricated thereon. The transistor device 100 also includes oxide spacers 110, which are used during the formation of the lightly doped drain (LDD) regions. In this example, the substrate is a P-type substrate (but of course, it can be an N-type substrate as illustrated by the parenthesis), and the diffusion regions 104 that define the source and drain are implanted with N+ impurities. In addition, the gate structure 109 is an N+ impurity region. During the normal operation of the LDD transistor device 100, a gate capacitance (Cgate) is established across the gate oxide 108. A significant component of total capacitance is the parasitic junction capacitance (C1) that is created at the induced depletion region between the source/drain and substrate interface.
As pictorially illustrated, the parasitic capacitance created between the source/drain and the substrate are shown as CJ1, and CJ2. Therefore, the total capacitance is approximately equal to xe2x80x9cCtotal=Cgate+CJ1+CJ2.xe2x80x9d Although a gate capacitance Cgate is required for the normal operation of the LDD transistor device 100, the presence of the parasitic capacitance CJ1 and C2 has a detrimental impact upon the speed that the transistor can switch during a logic transition. That is, each time the transistor device switches between a logic state, the source/drain junction parasitic capacitance must be charged and discharged, which can unfortunately slow down the functionality of a high performance circuit.
For ease of understanding, reference is now drawn to FIG. 1B in which the junction capacitance CJ between the diffusion regions 104 and the substrate 102 are pictorially illustrated about cross-section Axe2x80x94A. When an alternating current (AC) is applied between the junction formed by the diffusion regions 104 and the substrate 102, the depletion region 104xe2x80x2/102xe2x80x2 that is at the junction of the two materials responds to the AC signal. More specifically, the electric field (E) is plotted across the junction between the diffusion region 104 and the substrate 102 to illustrate how the parasitic capacitance CJ at the junction is approximated.
The electric field across the junction of the diffusion region 104 is plotted in a line 106a having a slope that is approximately proportional to the concentration of donor atoms (ND) of 104. In a like manner, the line 106b has a slope that is defined by the approximate concentration of acceptor atoms (NA) of the substrate 102. Once the electric field is plotted, the junction capacitance CJ is approximated to be 1/W, where W is the width of the depletion region. Therefore, if the donor concentration (ND)Of the diffusion region 104 increases, the slope 106a will also increase. Similarly, if the acceptor atom concentration (NA) of the substrate 102 increases, the slope 106b will also increase. In this example, the slope of line 106a is greater than the slope of line 106b because the donor concentration of the diffusion region 104 is higher than the concentration of the acceptor atoms in the substrate 102.
For the LDD transistor device 100 to operate properly, the concentration in the diffusion regions 104 must be greater than the concentration of the substrate 102. For example, the impurity concentration of P+ and N+ diffusion regions 104 are typically in the range of between about 1xc3x971019 atoms cmxe2x88x923 and 1xc3x971021 atoms cmxe2x88x923. The impurity concentration of the substrate 102 on the other hand, typically ranges between about 1xc3x971016 atoms cmxe2x88x923 and about 5xc3x971017 cmxe2x88x923. As a result, it is generally not possible to decrease the large parasitic junction capacitance CJ in an LDD transistor device, which necessarily limits its application in high performance applications (or simply slows down the circuit due to capacitive loading).
As mentioned above, another problem with the continued shrinking of transistor devices is the ability to meet tight backend processing thermal budget requirements. As is well known, a thermal budget is generally determined by calculating the total number of heat treatments and the time of those heat treatments that must be performed during the formation of the various layers of an integrated circuit device. By way of example, when an integrated circuit device requires a set number of layers, a thermal budget places a limitation on the heat treatments, such that dopant impurities do not over-diffuse into the substrate. For example, several types of dielectric deposition techniques require the application of heat annealing operations in order to adequately cure the dielectric materials. Such dielectric materials include spin-on glass (SOG), wherein the quality is improved by performing a certain type of heat anneal treatment. Additional heat treatments are also commonly required to cure certain types of conductive vias. Unfortunately, all of these heat treatments add to an already tight thermal budget.
FIG. 1C shows an ideal diffusion profile 113a which must be maintained after all of the backend thermal processing is performed. However, when the thermal budget is set too tight, the diffusion regions 104 may subsequently drop into the substrate down to profile lines 113b, thereby causing the depletion regions 114axe2x80x2 and 114bxe2x80x2 to be formed. As a result, the source and drain regions will no longer be isolated from one another, and will xe2x80x9cpunch-throughxe2x80x9d to electrically connect the source and drain. In other words, when punched-through occurs in a transistor device, the transistor will no longer operate in its intended manner. Unfortunately, the possibility of having the punched-through effect occurring in modern transistor devices is increasing as the demand for smaller and smaller transistor devices continues to grow. As a result, very stringent thermal budget requirements are placed on all backend processing, which therefore increase the complexity and cost of fabrication.
FIG. 1D is a pictorial illustration of the electric field (E) that is created when conduction between the source and drain occurs during an ON state. As further mentioned above, another problem with conventional LDD transistor devices is that of hot carrier generation, that arises from impact ionization at the drain junction. For ease of understanding, when a carrier is accelerated by an electric field across the channel length of the transistor device, the carrier is caused to impact onto an atom which thereby causes a release of an electron and a hole. Because the electric field that is generated at the drain and substrate interface is substantially perpendicular to the interface (with a large lateral component), the generated electron will be directed toward the gate electrode 109 and caused to travel through the gate oxide 108. One well known hot electron effect is the degrading damage to the gate oxide 108. Additionally, electrons may become trapped in the gate oxide 108, which causes undesirable variations in threshold voltage. For example, in NMOS transistor devices, the variations in threshold voltage can produce a reduction in drive current. As a result, the transistor device may ultimately fail to deliver the type of required performance.
FIG. 1E shows a prior art structure of a raised source/drain transistor device 120, which is known to ameliorate some of the hot carrier injection by altering the magnitude and direction of the electric field at the drain/substrate junction. The raised source/drain junctions are typically formed by depositing a crystalline or polycrystalline silicon over the substrate 102. The drain and source regions are therefore formed from diffusion regions 104a and 104b, and optionally, by the inclusion. of implants 114a and 114b. As compared to the LDD structure of FIG. 1A, the oxide sidewalls 110 are formed adjacent to the gate structure 109 and the source/drain deposited regions. Although the raised source/drain transistor structure of FIG. 1E has been successful in somewhat reducing hot carrier injection as described with reference to FIG. 1D, this structure still produces a very large parasitic junction capacitance (CJ) between the interface of the substrate 102 and the drain and source regions. In addition, if the thermal budget is not controlled carefully using precision techniques, there is also a possibility for the drain and source implants to further diffuse into the substrate and potentially produce a punched-through structure, such as that of FIG. 1C.
In view of the foregoing, there is a need for a semiconductor transistor structure that produces a low junction capacitance, enables for a more generous thermal budget, and is more resistant to hot carrier injection damage. Further, there is a need for methods of manufacturing new transistor structures which will enable the reduction in junction capacitance, enable a relaxation of thermal budget constraints, and enables a reduction in hot carrier generation.
Broadly speaking, the present invention fills these needs by providing semiconductor transistor structures that have substantially decreased junction capacitance, relaxed thermal budget parameters, and are more resistant to hot carrier damage. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, a computer readable medium or a method. Several inventive embodiments of the present invention are described below.
In one embodiment, a semiconductor transistor structure that is defined on a substrate is disclosed. The substrate has an active region that is isolated by shallow trench isolation oxide. The semiconductor transistor structure includes a gate stack that is disposed over a gate oxide that is in turn disposed over the active region of the substrate. A pair of shallow trenches are defined on either side of the gate stack. An intrinsic silicon material is disposed within the pair of shallow trenches up to a top surface of the gate stack and the shallow trench isolation oxide. The semiconductor transistor structure further includes source and drain implanted impurities that are defined in an upper portion of the intrinsic silicon material. The upper portion is configured to extend down into the intrinsic silicon material to a target diffusion level that is just below the gate oxide of the gate stack.
In another embodiment, a MOSFET structure is disclosed. The MOSFET structure includes a gate stack that is disposed over a gate oxide that is in turn disposed over an active region of a substrate. A pair of shallow trenches are defined on either side of the gate stack, and an intrinsic silicon material is disposed within the pair of shallow trenches up to a top surface of the gate stack. The MOSFET structure further includes source and drain implanted impurities that are defined in an upper portion of the intrinsic silicon material. The upper portion is configured to extend down into the intrinsic silicon material to a target diffusion level that is just below the gate oxide of the gate stack.
In yet another embodiment, a method for making a MOSFET structure having reduced parasitic junction capacitance is disclosed. The method includes: (a) forming shallow trench isolation regions in a substrate to define an active region; (b) forming a gate stack over the active region; (c) implanting lightly doped drain impurities into the active region on either side of the gate stack; (d) forming oxide sidewalls around the gate stack; (e) forming shallow trenches in the active region on either side of the gate stack, the shallow trenches are configured to remove most of the implanted lightly doped drain impurities except for a portion of impurities that lie under the oxide sidewalls; (f) depositing an intrinsic silicon into the shallow trenches up to at least a topmost level of the gate stack; and (g) implanting source drain impurities over the intrinsic silicon and the gate stack, the implanted impurities being configured to partially diffuse into the intrinsic silicon such that an electrical connection can be made to the portion of impurities of the lightly doped drain impurities that lie under the oxide sidewalls.
As will be further appreciated upon studying the detail description and drawings of the claimed embodiments, the disclosed transistor structure is configured to substantially reduce the parasitic junction capacitance, relax the thermal budget requirements during fabrication of backend operations, and reduce hot carrier damage (due to a reduction in lateral electric field). It should also become apparent that having such a reduced parasitic junction capacitance makes application of the disclosed transistor structure in ESD devices very beneficial (due to a large decrease in capacitive loading). Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.